using modelsim5.8 for Simulated and synthesized the design electronic manufacturing PCB assembly

using modelsim5.8 for Simulated and synthesized the design
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using modelsim5.8 for Simulated and synthesized the design
using modelsim5.8 for Simulated and synthesized the design

ModelSim 5.8 – EWSThis document is intended to help you set up your ModelSim environment on the EWSlinux stations. This procedure may be used to setup ModelSim on the EL231 labs once theSE version is installed. (The paths will of course be different.)1.Log into a EWS linux machine.a.You may SSH into one from EL231 using PuTTY just remember to enableX forwarding.2.Run your ece412 or ece412_G# script to set up the proper paths for ModelSim3.Create a dir where you would like your work to be simulated./nmnt/work1/ece412/kkielty2/testSim - as an example4.Open ModelSim by running
‘vsim’
a.ModelSim starts up in the directory from which you ran its command. It iscritical that you change into your working directory every time you startModelSim if it does not open there.5.Create the necessary librariesa.First build a library for your work by right clicking in the “Library” pane onthe left and selecting “
new->Library

Abstract:
A time-domain RS (Reed-Solomon) encoder was studied in this paper. Firstly analyzed coding theory of RS codes under the finite field, and focuses on the implementations of constant coefficients parallel multiplier under regular basis. On this basis, designed the encoder of RS (255,223) symmetrical structure in the Quartus7.0 build environment using the symmetry of polynomial coefficients, and use Matlab to prepare RS encoder debug and procedures verification, finally, obtained simulation results with the ModelSim5.8. The results show that the encoder is in good condition, and speed and occupancy characteristics of the hardware resources are limited compared with the existing type design.
Published in: Advanced Computer Control (ICACC), 2010 2nd International Conference on
Date of Conference: 27-29 March 2010
Date Added to IEEE Xplore: 17 June 2010
ISBN Information:

INSPEC Accession Number: 11502510
DOI: 10.1109/ICACC.2010.5486970
Publisher: IEEE
Conference Location: Shenyang, China
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Alerts
MOdelsim5.8 will be released soon.
there is a memory window in it.
and more coverage features.
I. Introduction
RS code is short for Reed-Solomon encoder, which is a kind of non-binary BCH codes, and is particularly applicable in correcting burst errors. Since I.S. Reed and G. Solomn proposed RS code in the paper determining constant research and improvement of their algorithm, with the purpose to increase throughput and reduce hardware resources and identify suitable VLSI implementation structure.

Using Incisive/NCSIM you can write models the way you suggested, using SystemC
constructs at the boundary and coding the functionality in C or C++. You can
load objects dynamically. You can use STL provided that you are using a
version of Incisive/NCSIM in which the SystemC library was compiled using
STL--older versions did not and you may have trouble if you mix old and new
styles. SystemC uses QT (I assume that means QuickThreads) internally--I don't
know what happens if you link in another QT implementation on top of it. The
graphics library should work fine--our DAC demo used X and the graphics worked
in both NCSIM and OSCI.

Abstract
Data encryption has become a crucial need for almost all data transaction application due to the large diversity of the remote information exchange. A huge value of sensitive data is transferred daily via different channels such as e-commerce, electronic banking and even over simple email applications. Advanced Encryption Standard (AES) algorithm has become the optimum choice for various security services in numerous applications. Therefore, many researches get focused on that algorithm in order to improve its efficiency and performance. This paper presents a survey about the cutting edge research conducted for the AES algorithm issues and aspects in terms of developments, implementations and evaluations. The contribution of this paper is targeted toward building a base for future development and implementation of the AES algorithm. It also opens door for implementing the AES algorithm using some machine learning techniques.

My Modelsim libraries are compiled.I have the
unisim,simprim,XilinxCorelib libraries compiled and they are under the
directory

C:\modeltech5.7g\xilinx_libs\unisim
C:\modeltech5.7g\xilinx_libs\simprim
C:\modeltech5.7g\xilinx_libs\XilinxCoreLib

Earlier the libraries were pointing to Xilinx Libraries and hence I
was seeing those errors.Now I see new errors like...

# ** Error: inrom_translate.vhd(641): Unknown identifier: init.
###### inrom_translate.vhd(653): INIT => '0'
# ** Error: inrom_translate.vhd(653): Unknown identifier: init.
###### inrom_translate.vhd(665): INIT => '0'
# ** Error: inrom_translate.vhd(665): Unknown identifier: init.
###### inrom_translate.vhd(1936): INIT => '0'
# ** Error: inrom_translate.vhd(1936): Unknown identifier: init.
###### inrom_translate.vhd(1948): INIT => '0'
# ** Error: inrom_translate.vhd(3531): Unknown identifier: x_roc
###### inrom_translate.vhd(3533): port map (O => GSR);
# ** Error: inrom_translate.vhd(3533): Unknown component name
###### inrom_translate.vhd(3534): NlwBlockTOC : X_TOC
# ** Error: inrom_translate.vhd(3534): Statement cannot be labeled.
# ** Error: inrom_translate.vhd(3534): Unknown identifier: x_toc
###### inrom_translate.vhd(3535): port map (O => GTS);
# ** Error: inrom_translate.vhd(3535): Unknown component name
###### inrom_translate.vhd(3537): end Structure;
# ** Error: inrom_translate.vhd(3537): VHDL Compiler exiting
# ERROR: C:/Modeltech_5.7g/win32/vcom failed.

Thanks for any ideas/help,

Sridhar

Vikram Pasham wrote in message
news:<41496A9A.3204C56B@xilinx.com>...
> Looks like Simprim libraries are missing which includes components like
> x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files
> have these libraries included. Unisim libraries are behavioral models while
> Simprim libraries are gate level models. Did you compile these libraries?
>
> This answer record will guide you on doing backannotated simulations.
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10177
>
> Regards
> Vikram
>
> Sridhar Hegde wrote:

> > Hi,
> >
> > I am designing a simple ROM in VHDL and following is the code for
> > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
> > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
> > design(Implementation process).
> >
> > When I use the test bench created by HDL bencher to see the results,
> > in Modelsim, a behavioral simulation shows be proper results but a
> > post translate simulation or anything beyond that like a Post Map or a
> > Post place and route simulation show a U on all output pins and
> > Modelsim gives me a number of warnings about "Unbound components"
> > shown below..
> >
> > Im stuck at this design phase and would appreciate any help from the
> > VHDL gurus out there...Heres the code:-
> >
> > -----------------------------------------------------------------------
> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > -- Uncomment the following lines to use the declarations that are
> > -- provided for instantiating Xilinx primitive components.
> > --library UNISIM;
> > --use UNISIM.VComponents.all;
> >
> > entity inrom is
> > Port ( en : in std_logic;
> > clk : in std_logic;
> > dout : out std_logic_vector( 15 downto 0);
> > valid : out std_logic; --valid data is present on output when 1
> > reset : in std_logic
> > );
> > end inrom;
> >
> > architecture rtl of inrom is

> > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
> > 0);
> > signal myarray : array_rom;
> > signal valid_sig:std_logic;
> > signal dout_sig : std_logic_vector(15 downto 0);
> > signal clk2: std_logic;
> >
> > begin
> >
> > myarray(0) <= x"0000";
> > myarray(1) <= x"0000";
> > myarray(2) <= x"0000";
> > myarray(3) <= x"003C";
> > myarray(4) <= x"0000";
> > myarray(5) <= x"0000";
> > myarray(6) <= x"0064";
> > myarray(7) <= x"0000";
> > myarray(8) <= x"0000";
> > myarray(9) <= x"000A";
> > myarray(10) <= x"0000";
> > myarray(11) <= x"0000";
> > myarray(12) <= x"003C";
> > myarray(13) <= x"0000";
> > myarray(14) <= x"0000";
> > myarray(15) <= x"0064";
> >
> > process( reset,clk)
> > variable romvar:natural range 0 to 15;
> >
> > begin
> > if reset = '1' then
> > dout_sig <= (others=>'0');
> > valid_sig <='0';
> > romvar :=0;

> > elsif (clk'event and clk='1') then
> > if en='1' then
> > dout_sig <= myarray (romvar);
> > valid_sig<='1';
> > romvar :=romvar + 1;
> > else
> > dout_sig <= myarray (romvar);
> > valid_sig<='0';
> > end if;
> > end if;
> > end process;
> >
> > dout <= dout_sig;
> > valid <=valid_sig;
> > end rtl;
> > -------------------------------------------------------------------------
> > Warnings given by Modelsim:

> > do inromtbw.ndo
> > # ** Warning: (vlib-34) Library already exists at "work".
> > ###### inrom_translate.vhd(443): );
> > # WARNING[1]: inrom_translate.vhd(443): No default binding for
> > component: "x_mux2". (No entity named "x_mux2" was found)
> > ###### inrom_translate.vhd(455): );
> > # WARNING[1]: inrom_translate.vhd(455): No default binding for
> > component: "x_ff". (No entity named "x_ff" was found)
> > ###### inrom_translate.vhd(468): );
> > # WARNING[1]: inrom_translate.vhd(468): No default binding for
> > component: "x_xor2". (No entity named "x_xor2" was found)
> > ###### inrom_translate.vhd(472): );
> > # WARNING[1]: inrom_translate.vhd(472): No default binding for
> > component: "x_zero". (No entity named "x_zero" was found)
> > ###### inrom_translate.vhd(476): );
> > # WARNING[1]: inrom_translate.vhd(476): No default binding for
> > component: "x_one". (No entity named "x_one" was found)
> > ###### inrom_translate.vhd(714): );
> > # WARNING[1]: inrom_translate.vhd(714): No default binding for
> > component: "x_lut2". (No entity named "x_lut2" was found)
> > ###### inrom_translate.vhd(2994): );
> > # WARNING[1]: inrom_translate.vhd(2994): No default binding for
> > component: "x_lut3". (No entity named "x_lut3" was found)
> > ###### inrom_translate.vhd(3128): );
> > # WARNING[1]: inrom_translate.vhd(3128): No default binding for
> > component: "x_lut4". (No entity named "x_lut4" was found)
> > ###### inrom_translate.vhd(3203): );
> > # WARNING[1]: inrom_translate.vhd(3203): No default binding for
> > component: "x_or2". (No entity named "x_or2" was found)
> > ###### inrom_translate.vhd(3341): );
> > # WARNING[1]: inrom_translate.vhd(3341): No default binding for
> > component: "x_tri". (No entity named "x_tri" was found)
> > ###### inrom_translate.vhd(3450): );
> > # WARNING[1]: inrom_translate.vhd(3450): No default binding for
> > component: "x_inv". (No entity named "x_inv" was found)
> > ###### inrom_translate.vhd(3533): port map (O => GSR);
> > # WARNING[1]: inrom_translate.vhd(3533): No default binding for
> > component: "x_roc". (No entity named "x_roc" was found)
> > ###### inrom_translate.vhd(3535): port map (O => GTS);
> > # WARNING[1]: inrom_translate.vhd(3535): No default binding for
> > component: "x_toc". (No entity named "x_toc" was found)
> > # vsim -lib work -t 1ps inromtbw
> > # Loading C:/Modeltech_5.7g/win32/std.standard
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_1164(body)
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_arith(body)
> > # Loading C:/Modeltech_5.7g/win32/std.textio(body)
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_textio(body)
> > # Loading C:/Modeltech_5.7g/win32/vital2000.vital_timing(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
> > # Loading C:/Modeltech_5.7g/win32/vital2000.vital_primitives(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
> > # Loading work.inromtbw(testbench_arch)
> > # Loading work.inrom(structure)
> > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
> > not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
> > not bound.

> > I can not use a Core generated ROM for this design due to some
> > restrictions I have in my other codes..Sorry for a rather long mail
> > and thanks in advance for any help!!
Reply Start a New Thread
Posted by Sridhar Hegde September 17, 2004
Hi Vikram,

This is my second message...I figured out the error and thought I
would reply here just in case some one else encountered the same issue

"Component is not bound/unbound" warnings come (as you said) when
Modelsim cant find the simprimlibraries.I had the libraries compiled
as I said but I was pointing to the wrong ones.

I needed to point to the one under C:\Xilinx6\vhdl\mti_se\simprim
instead of C:\Modelsim5.7g\xilinx_libs\simprim..

As soon as I fixed this, I got results as expected...Thanks for the
guidance.Now I can proceed with my design!!

Best Regards,
Sridhar

Vikram Pasham wrote in message
news:<41496A9A.3204C56B@xilinx.com>...
> Looks like Simprim libraries are missing which includes components like
> x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files
> have these libraries included. Unisim libraries are behavioral models while
> Simprim libraries are gate level models. Did you compile these libraries?
>
> This answer record will guide you on doing backannotated simulations.
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10177

> Regards
> Vikram
>
> Sridhar Hegde wrote:
>
> > Hi,
> >
> > I am designing a simple ROM in VHDL and following is the code for
> > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
> > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
> > design(Implementation process).
> >
> > When I use the test bench created by HDL bencher to see the results,
> > in Modelsim, a behavioral simulation shows be proper results but a
> > post translate simulation or anything beyond that like a Post Map or a
> > Post place and route simulation show a U on all output pins and
> > Modelsim gives me a number of warnings about "Unbound components"
> > shown below..
> >
> > Im stuck at this design phase and would appreciate any help from the
> > VHDL gurus out there...Heres the code:-

OBJECTIVE:
To work in a competitive and challenging work environment that fully
utilizes my capability. Want to contribute to the best of my ability
towards the growth and development of company and to pursue a challenging
and stewarding career.
EXPERIENCE:

Total work experience of 3 year till date in the field of VLSI.
07th aprilto30th September Working as a "Senior Testing Engineer" in VLSI
design with GREENSOFT TECHNOLOGIES, Trichy - Tamilnadu.
PROFESSIONAL SKILLS:
Good hands on RTL coding using VHDL /Verilog HDL .
Worked on RTL Simulation and Synthesis.
Worked on Programming FPGA Boards using Chip Scope-Pro.
Good knowledge in verification on test benches using VHDL/Verilog HDL.
Good Knowledge on ASIC Front end & Backend.
VLSI TOOLS AND METHODOLOGIES EXPOSURE:
Verilog coding and Simulation: ModelSim
Verilog Synthesis & FPGA Implementation: Xilinx-ISE
Programmable Board: Spartan Family and Virtex Family.
ACADEMIC QUALIFICATION:
Course Board of Name of the Year of Percentage/CGP
Examinations institution passing A
BE-ECE Anna Tagore Engineering 2010 63%
University college, Chennai.
XII State Board Hans Roever School, 2006 89.4%
Perambalur
X State Board Hans Roever School, 2004 89.4%
Perambalur
SOFTWARE SKILLS:
. Programming Language: VHDL, Verilog, Basics of C, ASIC Design,FPGA.
. Front end tools: Model Sim, Matlab, Xilinx.
. FPGA: Spartan-3E.
. Processors:8085
AREA OF INTEREST:
. Testing of VLSI circuits.
. Mixed CMOS Design.
. Low Power VLSI.
. ASIC Design.

PROJECTS:
1. SIMULTANEOUS DATA TRANSFER OVER PERIPHERAL BUS USING CDMA TECHNIQUE
Description:
This project is mainly developed for increasing the speed of chiplevel data
transmission.So I used CDMA technique in chiplevel data transmission to
reduce the time consumption of data transmission. CDMA (code division
multiple access) coding was developed using Verilog HDL (VHDL) according to
the architeture of CDMA. Modeled design has been synthesized and
implemented on FPGA family of Spartan 3E (XC3S500E) using Xilinx ISE.
Responsibilities:
Analyzed the architecture, developed the RTL code (Verilog HDL) based on
the architecture. Simulated the design using ModelSim. Analyzed the results
wheather it met required results or not. Language Used:
VHDL
Tools Required:
. Simulation: Model Sim-6.2.
. Synthesis: Xilinx ISE 9.1i.
2. A FRAMEWORK FOR CORRECTION OF MULTI-BIT SOFT
ERRORS
Description:
This project is mainly developed for multi-bit error detection by using
simple error detection codes and correct the error using data redundancy in
the memory hierarchy. This project is mainly used to reduce the power
consumption. With the continuous decrease in the minimum feature size and
increase in the chip density due to technology scaling, on-chip L2 caches
are becoming increasingly susceptible to multi-bit soft errors. The
increase in multi-bit errors could lead to higher risk of data corruption
and potentially result in the crashing of application programs.
Traditionally, the L2 caches have been protected from soft errors using
techniques such as: 1) error detection/correction codes; 2) physical
interleaving of cache bit lines to convert multi-bit errors into single-bit
errors; and 3) cache scrubbing. In this paper, we investigate in detail the
multi-bit soft error rates in large L2 caches and propose a framework of
solutions for their correction based on the amount of redundancy present in
the memory hierarchy. We investigate several new techniques for reducing
multi-bit errors in large L2 caches, in which, the multi-bit errors are
detected using simple error detection codes and corrected using the data
redundancy in the memory hierarchy.

Responsibilities:
Analyzed the architecture area consumed by the architecture and power
consumption becomes less. And the multi-bit errors are detected using
simple error detection codes and corrected using the data redundancy.
Simulated and synthesized the design using modelsim5.8 and synthesis
Xilinx9.1.
Language Used:
VHDL
Tools Required:
. Simulation: Model Sim-6.2.
. Synthesis: Xilinx ISE 9.1i.
3. A PROCESSOR-IN-MEMORY ARCHITECTURE FOR MULTIMEDIA
COMPRESSION
Description:
This paper is mainly developed to reducing the power and area for image
and video. We put forward design and development of a novel, low complexity
processor in memory (PIM) architecture for image and video compression. By
integrative a Novel processing element with SRAM, bandwidth is improved and
latency is greatly reduced. Through this paper we present PIM design
techniques for reduced power, area, and complexity for rapid deployment and
reduced cost. A design methodology is presented and followed by an analysis
of the processing element performance and capabilities. The architecture
executes a discrete cosine and wavelet transforms achieving higher output
and area consumption is very less.
Responsibilities:
Analyzed the architecture, simulated and synthesized the design using
modelsim and then checked whether the image and video compression have done
or not.

Language Used:
VHDL
Tools Required:
. Simulation: Model Sim-6.2.
. Synthesis: Xilinx ISE 9.1i.
4. LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY;
Description:
1.This paper enumerates low power, high speed design of flip-flop having
less number of transistors and only one transistor being clocked by short
pulse train which is true single phase clocking (TSPC) flip-flop.
2. Compared to Conventional flip-flop, it has 5 Transistors and one
transistor clocked, thus has lesser size and lesser power consumption. It
can be used in various applications like digital VLSI clocking system,
buffers, registers, microprocessors etc.
The analysis for various flip flops and latches for power dissipation and
propagation delays at 0.13 m and 0.35 m technologies is carried out.
The leakage power increases as technology is scaled down.
3.The leakage power is reduced by using best technique among all run time
techniques viz- MTCMOS. Thereby comparison of different conventional flip-
flops, latches and TSPC flip-flop in terms of power consumption,
propagation delays and product of power dissipation and propagation delay
with SPICE simulation results is presented.
Responsibilities:
Analyzed the architecture, simulated and synthesized the design using
modelsim and then checked whether the speed of design is high with low

power or not.
Language Used:
VHDL
Tools Required:
Simulation: ModelSim XE III 6.4
Synthesis :Xilinx9.1
CO-CURRICULAR ACTIVITIES:
. Organizer for Circuit debugging event in Ambitus'09(Department of ECE
and E&I).
. Participated in Rotary Youth Leadership Award (RYLA) program organized
by Rotary club of Madras West.
SPORTS ACTIVITIES:
. 2nd Prize -Cricket-College Level Tournament (2008).
. 1st Prize-Cricket-College Level Tournament (2010).

• Worked on Orion Battery Management system prominently used for HEV, PHEV, and EV
• Scrutinized components like motors, drivers, cell harness compatible to the 84 cell batteries specification, depending on its voltage generation, heat management and torque generation and, accordingly provide proper solutions

PERSONAL PROFILE:
Name : Manoj.G
Date of Birth : 17-5-1989
Gender : Male
Nationality : Indian
Marital Status : Single
Languages known : English(R/W/S), Tamil(R/W/S).
Permanent address : 106/c, venkatesapuram 6th street, perambalur-
621212.
DECLARATION:
I hereby declare that all the above mentioned statements and documents
furnished above are true and best to my knowledge and know they can be duly
submitted for verification as per employer will.

> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > -- Uncomment the following lines to use the declarations that are
> > -- provided for instantiating Xilinx primitive components.
> > --library UNISIM;
> > --use UNISIM.VComponents.all;

> > entity inrom is
> > Port ( en : in std_logic;
> > clk : in std_logic;
> > dout : out std_logic_vector( 15 downto 0);
> > valid : out std_logic; --valid data is present on output when 1
> > reset : in std_logic
> > );
> > end inrom;
> >
> > architecture rtl of inrom is
> >
> > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
> > 0);
> > signal myarray : array_rom;
> > signal valid_sig:std_logic;
> > signal dout_sig : std_logic_vector(15 downto 0);
> > signal clk2: std_logic;
> >
> > begin
> >
> > myarray(0) <= x"0000";
> > myarray(1) <= x"0000";
> > myarray(2) <= x"0000";
> > myarray(3) <= x"003C";
> > myarray(4) <= x"0000";
> > myarray(5) <= x"0000";
> > myarray(6) <= x"0064";
> > myarray(7) <= x"0000";
> > myarray(8) <= x"0000";
> > myarray(9) <= x"000A";
> > myarray(10) <= x"0000";
> > myarray(11) <= x"0000";
> > myarray(12) <= x"003C";
> > myarray(13) <= x"0000";
> > myarray(14) <= x"0000";
> > myarray(15) <= x"0064";
> >
> > process( reset,clk)
> > variable romvar:natural range 0 to 15;

> > begin
> > if reset = '1' then
> > dout_sig <= (others=>'0');
> > valid_sig <='0';
> > romvar :=0;
> >
> > elsif (clk'event and clk='1') then
> > if en='1' then
> > dout_sig <= myarray (romvar);
> > valid_sig<='1';
> > romvar :=romvar + 1;
> > else
> > dout_sig <= myarray (romvar);
> > valid_sig<='0';
> > end if;
> > end if;
> > end process;
> >
> > dout <= dout_sig;
> > valid <=valid_sig;
> > end rtl;
> > -------------------------------------------------------------------------
> > Warnings given by Modelsim:

> > do inromtbw.ndo
> > # ** Warning: (vlib-34) Library already exists at "work".
> > ###### inrom_translate.vhd(443): );
> > # WARNING[1]: inrom_translate.vhd(443): No default binding for
> > component: "x_mux2". (No entity named "x_mux2" was found)
> > ###### inrom_translate.vhd(455): );
> > # WARNING[1]: inrom_translate.vhd(455): No default binding for
> > component: "x_ff". (No entity named "x_ff" was found)
> > ###### inrom_translate.vhd(468): );
> > # WARNING[1]: inrom_translate.vhd(468): No default binding for
> > component: "x_xor2". (No entity named "x_xor2" was found)
> > ###### inrom_translate.vhd(472): );
> > # WARNING[1]: inrom_translate.vhd(472): No default binding for
> > component: "x_zero". (No entity named "x_zero" was found)
> > ###### inrom_translate.vhd(476): );
> > # WARNING[1]: inrom_translate.vhd(476): No default binding for
> > component: "x_one". (No entity named "x_one" was found)
> > ###### inrom_translate.vhd(714): );
> > # WARNING[1]: inrom_translate.vhd(714): No default binding for
> > component: "x_lut2". (No entity named "x_lut2" was found)
> > ###### inrom_translate.vhd(2994): );
> > # WARNING[1]: inrom_translate.vhd(2994): No default binding for
> > component: "x_lut3". (No entity named "x_lut3" was found)
> > ###### inrom_translate.vhd(3128): );
> > # WARNING[1]: inrom_translate.vhd(3128): No default binding for
> > component: "x_lut4". (No entity named "x_lut4" was found)
> > ###### inrom_translate.vhd(3203): );
> > # WARNING[1]: inrom_translate.vhd(3203): No default binding for
> > component: "x_or2". (No entity named "x_or2" was found)
> > ###### inrom_translate.vhd(3341): );
> > # WARNING[1]: inrom_translate.vhd(3341): No default binding for
> > component: "x_tri". (No entity named "x_tri" was found)
> > ###### inrom_translate.vhd(3450): );
> > # WARNING[1]: inrom_translate.vhd(3450): No default binding for
> > component: "x_inv". (No entity named "x_inv" was found)
> > ###### inrom_translate.vhd(3533): port map (O => GSR);
> > # WARNING[1]: inrom_translate.vhd(3533): No default binding for
> > component: "x_roc". (No entity named "x_roc" was found)
> > ###### inrom_translate.vhd(3535): port map (O => GTS);
> > # WARNING[1]: inrom_translate.vhd(3535): No default binding for
> > component: "x_toc". (No entity named "x_toc" was found)
> > # vsim -lib work -t 1ps inromtbw
> > # Loading C:/Modeltech_5.7g/win32/std.standard
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_1164(body)
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_arith(body)
> > # Loading C:/Modeltech_5.7g/win32/std.textio(body)
> > # Loading C:/Modeltech_5.7g/win32/ieee.std_logic_textio(body)
> > # Loading C:/Modeltech_5.7g/win32/vital2000.vital_timing(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
> > # Loading C:/Modeltech_5.7g/win32/vital2000.vital_primitives(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
> > # Loading work.inromtbw(testbench_arch)
> > # Loading work.inrom(structure)
> > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
> > not bound.

> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
> > not bound.
> >
> > I can not use a Core generated ROM for this design due to some
> > restrictions I have in my other codes..Sorry for a rather long mail
> > and thanks in advance for any help!!

Keywords

Cryptography Advanced Encryption Standard FPGA ASIC Machine Learning
Preview

Regarding coding the functionality in non-SystemC C/C++: The SystemC
objects (sc_signal, sc_in, ...) are visible in the NCSIM GUI/Tcl user
interface, just like Verilog or VHDL objects. The native C/C++ objects
generally are not, but they can be made available to the GUI/Tcl interface
through a class ncsc_viewable (not supported by OSCI) that we added.

a new library and a logical mapping to it”
c.In the Library Name field you may specify a name or simply leave it as‘work’d.In the Library Physical Name field insert the path to the directory youcreated in 3, ex. /nmnt/work1/ece412/kkielty2/testSime.Repeat this procedure for a library that you will call ‘unisim’. (path may besomething like /nmnt/work1/ece412/kkielty2/unisim)6.Compile the unisim librariesa.First you will need to move them to your Linux machine so that ModelSimcan see them. The files you want to move over are in the local Windowshard drive in the lab.i.C:\Xilinx\vhdl\src\unisims1.unisim_SMODEL.vhd2.unisim_VCOMP.vhd3.unisim_
VITAL.vhd4.unisim_VPKG.vhdii.C:\Xilinx\verilog\src\ise\1.unisim_comp.v b.Next you will need to compile them. In ModelSim click
“Compile->compile”
c.Select ‘unisim’ as the libraryd.Using CTRL select the 4 files you just copied and hit “
Compile”
. This maygive you errors. If you see these then simply compiles the files in this order:VCOMP, VPKG, VITAL, SMODELi.You probably don’t need SMODEL – disk space may be an issueii.Also compile in the verilog file. This is vitally important!

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