AHDL support Logic synthesis High levelsimulation

AHDL A good design tool will support Logic synthesis High levelsimulation

AHDL A good design tool will support Logic synthesis High levelsimulation
HDL Designer
HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.

FEATURES AND BENEFITS
Key Benefits

Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
Accelerates RTL Reuse
Extensive design checking rules and rulesets
Interactive HDL visualization and creation tools
Automatic documentation features and reporting
Intelligent debug and analysis
Concurrent design entry and checking
Design and Reuse

Quickly assess reused code quality and increase design understanding
Efficiently create RTL designs using text, tables, and graphics
Interactively manage design flow and all project data
Rapidly produce documentation
Accelerate IP repository population

HDL Works

HDL Works is a supplier of front-end VHDL / Verilog design tools, translators and an FPGA / PCB pin assignment verification tool.
HDL Works has over 15 years experience developing HDL tools.

All tools are available on Windows and Linux operating systems.

Join a HDL Works mailing list !
Join an HDL Works mailing list
Design & Verification Products
EASE Graphical HDL Design tool.
Combines block diagrams, state diagrams, truth tables and HDL code.
HDL Companion The SWISS Army knife for every HDL Design Engineer
It will give you a complete overview of any VHDL or Verilog design in seconds.
Features include verification, linting and HTML generation.
IO Checker When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task.
IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment.
Scriptum A text editor focused at VHDL and Verilog, using a Multiple Document Interface.
(Free of charge)
ConnTrace ConnTrace is used to verify the connections between various PCB's, Independent on how your PCBs are connected (backplanes, connectors and/or rear panels). ConnTrace will present a view of the connections in seconds.

In electronics, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of a HDL description into a netlist (a specification of physical electronic components and how they are connected together), which can then be placed and routed to produce the set of masks used to create an integrated circuit.
A hardware description language looks much like a programming language such as C; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.
HDLs form an integral part of electronic design automation (EDA) systems, especially for complex circuits, such as application-specific integrated circuits, microprocessors, and programmable logic devices.
Contents [hide]
1 Motivation
2 Structure of HDL
2.1 Comparison with control-flow languages
3 History
4 Design using HDL
5 Simulating and debugging HDL code
6 Design verification with HDLs
7 HDL and programming languages
8 High-level synthesis
9 Examples of HDLs
9.1 HDLs for analog circuit design
9.2 HDLs for digital circuit design
9.3 HDLs for printed circuit board design
10 See also
11 References
12 External links
Motivation[edit]
Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's law), circuit designers needed digital logic descriptions to be performed at a high level without being tied to a specific electronic technology, such as CMOS or BJT. HDLs were created to implement register-transfer level abstraction, a model of the data flow and timing of a circuit.[1]
There are two major hardware description languages: VHDL and Verilog. There are different types of description in them "dataflow, behavioral and structural". Example of dataflow of hdl:
library iEEE;
use iEEE.STD_LOGIC_1164.ALL;
use iEEE.STD_NUMERIC_STD.ALL;

entity not1 is
port(a:in STD_LOGIC;
b:out STD_logic);
end not1;

architecture behavioral of not1 is
begin
b <= not a;
end behavioral;
Structure of HDL[edit]
HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like concurrent programming languages, HDL syntax and semantics include explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages used in electric computer-aided design (CAD). HDL can be used to express designs in structural, behavioral or register-transfer-level architectures for the same circuit functionality; in the latter two cases the synthesizer decides the architecture and logic gate layout.
HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages, when they are more precisely classified as specification languages or modeling languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available.

HDL simulation software has come a long way since its early origin as a single proprietary product offered by one company. Today, simulators are available from many vendors at various prices, including free ones. For desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD,TarangEDA and others offer <$5000 USD tool-suites for the Windows 2000/XP platform. The suites bundle the simulator engine with a complete development environment: text editor, waveform viewer, and RTL-level browser. Additionally, limited-functionality editions of the Aldec and ModelSim simulator are downloadable free of charge, from their respective OEM partners (Microsemi, Altera, Lattice Semiconductor, Xilinx, etc.) For those desiring open-source software, there is Icarus Verilog, GHDL among others.
Beyond the desktop level, enterprise-level simulators offer faster simulation runtime, more robust support for mixed-language (VHDL and Verilog) simulation, and most importantly, are validated for timing-accurate (SDF-annotated) gate-level simulation. The last point is critical for the ASIC tapeout process, when a design database is released to manufacturing. (semiconductor foundries stipulate the usage of tools chosen from an approved list, in order for the customer's design to receive signoff status. Although the customer is not required to perform any signoff checking, the tremendous cost of a wafer order has generally ensured thorough design validation on the part of the customer.) The three major signoff-grade simulators include Cadence Incisive Enterprise Simulator, Mentor ModelSim/SE, and Synopsys VCS. Pricing is not openly published, but all three vendors charge $25,000-$100,000 USD per seat, 1-year time-based license.
FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor's device libraries. For designs targeting high-capacity FPGA, a standalone simulator is recommended, as the OEM-version may lack the capacity or speed to effectively handle large designs.
Below is a list of various HDL simulators.

There is a design tool that is being quietly adopted by FPGA engineers because, in many cases, it produces results that are better than hand-coded counterparts.

FPGAs keep getting larger, the designs more complex, and the need for high level design (HLD) flows never seems to go away. C-based design for FPGAs has been promoted for over two decades and several such tools are currently on the market. Model-based design has also been around for a long time from multiple vendors. OpenCL for FPGAs has been getting lots of press in the last couple of years. Yet, despite all of this, 90+% of FPGA designs continue to be built using traditional Verilog or VHDL.

No one can deny the need for HLD. New FPGAs contain over 1 million logic elements, with thousands of hardened DSP and memory blocks. Some vendor's devices can even support floating-point as efficiently as fixed-point arithmetic. Data convertor and interface protocols routinely run at multiple GSPS (giga samples per second), requiring highly parallel or vectorized processing. Timing closure, simulation, and verification become ever-more time-consuming as design sizes grow. But HLD adoption still lags, and FPGAs are primarily programmed by hardware-centric engineers using traditional hardware description languages (HDLs).

The primary reason for this is quality of results (QoR). All high-level design tools have two key challenges to overcome. One is to translate the designer's intent into implementation when the design is described in a high-level format. This is especially difficult when software programming languages are used (C++, MATLAB, or others), which are inherently serial in nature. It is then up to the compiler to decide by how much and where to parallelize the hardware implementation. This can be aided by adding special intrinsics into the design language, but this defeats the purpose. OpenCL addresses this by having the programmer describe serial dependencies in the datapath, which is why OpenCL is often used for programming GPUs. It is then up to the OpenCL compiler to decide how to balance parallelism against throughput in the implementation. However, OpenCL programming is not exactly a common skillset in the industry.

The second key challenge is optimization. Most FPGA hardware designers take great pride in their ability to optimize their code to achieve the maximum performance in a given FPGA, in terms of design Fmax, or the achievable frequency of the system clock data rate. This requires closing timing across the entire design, which means setup and hold times have to be met for every circuit in the programmable logic and every routing path in the design. The FPGA vendors provide automated synthesis, fitting, and routing tools, but the achievable results are heavily dependent upon the quality of the Verilog and/or VHDL source code. This requires both experience and design iteration. The timing closure process is tedious and sometime compared to "Whack-a-Mole," meaning that when a timing problem is fixed in one location of the design, a different problem often surfaces at another location.

HVL Compilers

Specman : This compiler debugger simulator is for e language, the most popular of all the HVL's
Vera : This compiler simulator is for VERA language, lately lot of good features have been added both to compiler and also VERA language.
TestBuilder : This is set of free C++ class packages for writing HVL testbenches. I have used this, and found it to be useful for writing testbenches, but then it is no way close to Specman.
SystemC SCV : Testbuilder team added verification capability to systemC. I personally feel this is better then Testbuilder.

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Verilog Simulators

Verilog-XL : This is the most standard simulator in the market, as this is the sign off simulator.
NCVerilog : This is the compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations.
VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools.
Aldec : This simulator from Aldec supports VHDL, Verilog, SystemC, SystemVerilog, PSL. You name it and it supports it. I could not verify the SV testbench support, other than that everything else looks same as Modelsim. You can even use it to replace your existing Modelsim/VCS/NCverilog licenses.
Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. A $100 version is available, but I wonder what good this can do to Students ?
Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.

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Free Simulators

Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well. All my tutorials are compiled on this compiler.

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VCD Viewer

nWave : One of the best VCD viewer, with support for large VCD dumps.
Undertow : Undertow waveform viewer.
GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
Dinotrace : Freeware VCD viewer from veritools

FPGA Design Creation and Simulation
Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
The design flow manager evokes 120+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more.
ActiveHDL_graphic
Top Features and Benefits
Project Management
Unified Team-based Design Management maintains uniformity across local or remote teams
Configurable FPGA/EDA Flow Manager interfaces with 120+ vendors tools allows teams to remain on one platform throughout FPGA development
Graphical/Text Design Entry
Quickly deploy designs by using Text, Schematic and State Machine
Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard
Simulation and Debugging
Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog(Design) and SystemC
Ensure code quality and reliability using graphically interactive debugging and code quality tools
Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools

OPENCORES: Tools

Introduction

OpenCores is the world largest community focusing on open source development targeted for hardware. Designing IP cores, is unfortunately not as simple as writing a C program. A lot more steps are needed to verify the cores and to ensure they can be synthesized to different FPGA architectures and various standard cell libraries.

Open Source EDA tools

There are plenty of good EDA tools that are open source available. The use of such tools makes it easier to collaborate at the opencores site. An IP that has readily available scripts for an open source HDL simulator makes it easier for an other person to verify and possibly update that particular core. A test environment that is built for a commercial simulator that only a limited number of people have access to makes verification more complicated.

Icarus Verilog Simulator

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the &qout;vvp&qout; command. For synthesis, the compiler generates netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005.

Icarus web site

Verilator

Verilator is a free Verilog HDL simulator. It compiles synthesizable Verilog into an executable format and wraps it into a SystemC model. Internally a two-stage model is used. The resulting model executes about 10 times faster than standalone SystemC.

Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. Therefor we have chosen this tool to be used in the verification environment for the OpenRISC processor.

Verilator web site
GHDL VHDL simulator

GHDL implements the VHDL87 (common name for IEEE 1076-1987) standard, the VHDL93 standard (aka IEEE 1076-1993) and the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000). The VHDL version can be selected with a command line option.

GHDL web site

EMACS - text editor

GNU Emacs is an extensible, customizable text editor—and more.

Very good support for both Verilog HDL and VHDL editing.

Emacs web site

Fizzim is a FREE, open-source GUI-based FSM design tool

The GUI is written in java for portability. The backend code generation is written in perl for portability and ease of modification.

Features:

GUI:

Runs on Windows, Linux, Apple, anything with java.
Familiar Windows look-and-feel.
Visibility (on/off/only-non-default) and color control on data and comment fields.
Multiple pages for complex state machines.
"Output to clipboard" makes it easy to pull the state diagram into your documentation.
Backend:

Verilog code generation based on recommendations from experts in the field.
Output code has "hand-coded" look-and-feel (no tasks, functions, etc).
Switch between highly encoded or onehot output without changing the source.
Registered outputs can be specified to be included as state bits, or pulled out as independent flops.
Mealy and Moore outputs available.
Transition priority available.
Automatic grey coding available.
Code and/or comments can be inserted at strategic places in the output - no need to "perl" the output to add your copyright or `include

PlanAhead Design and Analysis Tool
A faster, more efficient design solution to help achieve your performance goals.

PlanAhead™ offers an RTL to bit stream design flow with new and improved user interface and project management capabilities. With PlanAhead software, you can view implementation and timing results to easily analyze critical logic, and make targeted decisions to improve design performance with floorplanning, constraint modification, and many Synthesis and Implmentation settings. It helps you make tradeoffs between RTL Coding and Synthesis and Implementation, with extensive design exploration and analysis features.

With convenient access through integration with the ISE Project Navigator, PlanAhead software extends the methodology of the logic design flow to help you get the most out of your design through floorplanning, multiple implementation runs, hierarchy exploration, quick timing analysis, and block based implementation.

PlanAhead software also provides an easy and convenient method of creating & inserting the ChipScope™ Pro debug cores to simplify the process of on-chip verification.

Design Entry for RTL, IP, EDK and DSP Designs Provides a comprehensive cockpit for creating and verifying RTL designs in either Verilog or VHDL, including access to the Xilinx IP catalog through CORE Generator integration. PlanAhead includes an RTL technology view, where a fast elaboration of RTL sources will yield access to a schematic view, resource and power estimation. Management of synthesis runs is achieved through integration with XST.
Offers integration with Xilinx Platform Studio (XPS) and System Generator for DSP designs. Create and add XPS and DSP subsystems to a project through the .xmp and .sgp source type. Integration support also includes importing and converting ISE® tools projects to PlanAhead design tool projects and generating files from the XPS tool appropriately in the synthesis and implementation flow tools.
Design Verification Integrated with ISE Simulator to perform behavioral and functional verification of HDL code and IP at various stages of the design. PlanAhead also allows you to choose Mentor Graphics simulators as the target simulator in the project settings, enabling multiple simulation filesets with their own sets of properties. Simultaneously create and maintain multiple simulation configurations which could vary in areas such as the testbench being used or other simulation properties.
Simplified Pin Planning Provides features to help you simplify the complexities of pin assignments with an environment for fully automatic or semi-automated assignment of I/O ports to physical Package Pins.
Synthesis and Implementation Management Includes an exploration tool to help with experimentation of HDL, tool options, and floorplanning trials to achieve design closure. By managing multiple runs, PlanAhead allows you to execute multiple trials based on strategies the user defines or predefined strategies shipped as factory defaults. In a Linux environment, PlanAhead software provides the ability to execute runs in parallel on remote hosts.
Design Analysis and Floorplanning Provides extensive capabilities to help designers achieve design closure. This includes a GUI with comprehensive cross-probing to analyize your designs and track issues such as timing violations and DRCs and then trace them back to schematics, netlists and constraints. This allows designers to experiment with physical constraints such as pblocks (area groups) and location constraints for cell instances.

Allegro Design Entry HDL Basics
Enroll Online Subscription Online Courses Instructor-Led Schedule
Length : 1 days

Course Description

This course introduces you to Allegro® Design Entry HDL. In this course, you learn how to build basic schematic library parts using the Part Developer. You also create a flat, multi-sheet schematic design.

Learning Objectives

After completing this course, you will be able to:

Set up a Library Project
Create basic schematic parts using the Part Developer
Set up a Design Project
Create a flat, multi-sheet schematic
Copy pages from other designs
Assign reference designators and generate a netlist for the Allegro PCB Editor
Check the schematic for errors
Cross-reference multi-sheet nets
Generate a bill of materials
Copy an existing project and perform engineering changes
Software Used in This Course

Allegro Design Authoring PS2000
Allegro PCB Librarian PX3500
Software Release(s)

SPB172

Modules in this Course

Setting Up a Library Project
The Symbol View
The Chips View
The Part Table View
Testing the Part
More Part Building
Setting Up a Design Project
Design Entry and Packaging
Engineering Changes
Audience

This course is for anyone who needs to draw schematics using Allegro Design Entry HDL. If you are using the Allegro Design Entry CIS or the OrCAD® Capture tool, then see the Allegro Design Entry Capture (OrCAD Capture) course instead.
Prerequisites

This course has no prerequisites.

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